A power transistor may usually be responsible for final output in a power circuit to implement power output. In a high frequency scenario, a direct current-direct current (DC-DC) converter may implement high efficiency output using a stacked power transistor.
Referring to FIG. 1, FIG. 1 is a schematic diagram of a power transistor bias circuit based on a stacked power transistor. As shown in FIG. 1, the stacked power transistor circuit may include a P-type Metal Oxide Semiconductor (MOS) transistor MP 1, a P-type MOS transistor MP 2, an N-type MOS transistor MN 1, an N-type MOS transistor MN 2, a ½ power rail bidirectional voltage regulator, a P-type field effect transistor driver module, an N-type field effect transistor driver module, a capacitor 1, and a capacitor 2. A source of the MP 1 is connected to a power source (Power Voltage Device (PVDD)). A drain of the MP 1 is connected to a source (for example, a VPCAS node) of the MP 2. A drain of the MP 2 is connected to a drain (for example, an LX node) of the MN 2. A source of the MN 2 is connected to a drain (for example, a VNCAS node) of the MN 1. A source of the MN 1 is connected to a power ground (PGND). The P-type field effect transistor driver module is connected to a gate of the MP 1, and the N-type field effect transistor driver module is connected to a gate of the MN 1. A Pulse Width Modulation (PWM) controller is configured to control the P-type field effect transistor driver module to input a drive signal PG to the gate of the MP 1, and control the N-type field effect transistor driver module to input a drive signal NG to the gate of the MN 1. The ½ power rail bidirectional voltage regulator is configured to input a bias voltage VMID=½ (PVDD+PGND) to a gate of the MP 2 and a gate of the MN 2 based on a power voltage of the PVDD and a power ground voltage of the PGND, and use the bias voltage as a power domain voltage of the P-type field effect transistor driver module and the N-type field effect transistor driver module. In a high-frequency DC-DC converter, the bias voltage may be used to improve parameters such as stability of a control loop and reliability of the power transistor.
However, an existing problem is that in the circuit shown in FIG. 1, the ½ power rail bidirectional voltage regulator provides a same bias voltage for both the gate of the MP 2 and the gate of the MN 2. Therefore, a switch action of a switching transistor of an upper transistor (MP 1) not only affects a value of the bias voltage input to the gate of the MP 2 but also affects the bias voltage input to the gate of the MN 2. Similarly, a switch action of a switching transistor of a lower transistor (MN 1) not only affects a value of the bias voltage input to the gate of the MN 2, but also affects the bias voltage input to the gate of the MP 2.